1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to methods of forming line ends in a material in an IC and a memory cell including the line ends.
2. Background Art
Memory used in integrated circuit (IC) chips can come in a variety of forms such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, etc. In order to produce the highest performing memory cells within a specific cell size it is necessary to increase the device widths as much as possible. As the device widths are increased, the width of the isolation regions (e.g., shallow trench isolation (STI)) between the active areas of the device is decreased. The minimization of the width of the isolation regions is not limited by the ability to print the active region pattern, but from the ability to place two polysilicon conductor (polyconductor or PC) line ends end-to-end (facing each other or otherwise) on the isolation region. Thus, the performance of a memory cell is directly influenced by the tip to tip space that can be achieved between PC line ends.
The ability to pattern a small space between PC line ends has both lithographic and etch limitations. The etch limitations come from the fact that during the trim step (i.e., the process in which the gate critical dimension (CD) that was printed in photoresist is reduced to that which is needed in the final polysilicon) the line ends trim more than the gates. In particular, as shown in FIG. 1, a specific PC line end 2 may be targeted to be, for example, 100 nm past an active region 4 into an isolation region 8 (scenario A both sides and scenario B, left side only) or make good contact with contact layer 6 (scenario B, right side only), but due to limitations of the resist, trim processing and rounding, PC line end 2 does not end up being 100 nm past the active region 4 or contact layer 6.
There are many methods which are being pursued in the industry to enable the tighter PC line end spacing. For example, one popular approach includes a double exposure-double etch scheme. In this case, as shown in FIG. 2, a polyconductor (PC) 12 is exposed and etched over an active region 14 and fully across an isolation region 16 to print a gate 18 (intersection of PC 12 and active region 14), and then another exposure and etch, shown in FIG. 3, is used to remove polyconductor 12 over the isolation region 16 to form line ends 22 and, hence, the devices. The approach allows the etch step for opening line ends 22 to be completely directional (no trim) and also creates PC tips that are relatively rectangular. While attaining the necessary sizes and precision, however, the cost incurred is significant because of the need for two exposures and two etches for one level.
A second approach includes using a double exposure with a single etch. While this approach does not eliminate the etch effects, it allows for a smaller line end space to be printed in resist, if the illumination is optimized for the second exposure. An optimized version of this approach exposes the PC using an alternating phase shift masks (Alt PSM) scheme and a block/trim mask to print the space between the line ends.